Scalable planar DMOS transistor structure and its fabricating methods

摘要

The scalable planar DMOS transistor structure of the present invention comprises a scalable source region surrounded by a planar gate region. The scalable source region comprises a p-base diffusion region being formed in a n^- epitaxial semiconductor layer through a ring-shaped implantation window, a n⁺ source diffusion ring being formed in a surface portion of the p-base diffusion region through the ring-shaped implantation window, a p⁺ contact diffusion region being formed in a middle semiconductor surface portion through a self-aligned implantation window being surrounded by the ring-shaped implantation window, and a self-aligned source contact window being formed on the p⁺ contact diffusion region and the n⁺ source diffusion ring surrounded by a sidewall dielectric spacer. The planar gate region comprises a patterned heavily-doped polycrystalline-silicon gate layer being formed on a gate dielectric layer and capped locally with or without metal silicide layers.