CLOCK REPRODUCING DEVICE AND CLOCK SIGNAL REPRODUCING METHOD

摘要

PROBLEM TO BE SOLVED: To assure the initial synchronization of a PLL circuit. SOLUTION: This clock reproducing device has a phase locked loop for receiving a transmitted data signal and generating an output clock signal, and a frequency detection circuit 10 for receiving output clock and reference clock and generating a frequency error signal, and adds the frequency error signal to the phase error signal of the phase locked loop when the frequency error signal is large.