N+ POLYSILICON ON HIGH-K DIELECTRIC SEMICONDUCTOR DEVICES

摘要

Semiconductor devices with high-k dielectric layers and methods of their fabrication are provided. An n-type well region (304) is formed within a semiconductor body (302). A threshold voltage adjustment implant is performed by implanting a p-type dopant into the n-type well region to form a counter doped region (307). A high-k dielectric layer (308) is formed over the device (300). A polysilicon layer (310) is formed on the high-k dielectric layer and doped n-type. The high-k dielectric layer and the polysilicon layer are patterned to form polysilicon gate structures. P-type source/drain regions (306) are formed within the n-type well region.