摘要 |
<p>PROBLEM TO BE SOLVED: To enable writing at a low drain-source bias voltage by negatively charging a floating gate of an EPROM and an EEPROM, using channel- originated secondary electron injection. SOLUTION: A semiconductor has a substrate 100, a source region 110, a drain region 120, a channel 130, a floating gate 140, and a control gate 160. The floating gate 140 is electrically isolated from the substrate 100 and the control electrode 160 by a first silicon oxide film layer 150 and a second silicon oxide film layer 170, respectively. To inject electrons into the floating gate 140 by using a CISEI mechanism, a bias voltages of 1.1 V<=VDS<=3.3 V and -3 V<=VBS<=-0.5 V are applied to the device. The value of VCS necessary for negatively charging the floating gate 140 depends on the capacitive coupling between the floating gate 140 and the control gate.</p> |