SYNCHRONOUS MEMORY DEVICE

摘要

PURPOSE: A synchronous memory device is provided to achieve a high-speed access operation because an address signal pre-decoded by a row-pre-decoding circuit is not limited by a clock signal. CONSTITUTION: A memory cell array includes many memory cells arranged in a matrix-type of columns and rows. Row selection lines correspond to the rows. A control circuit controls a time-point of an activation and a non-activation of the row selection lines according to an external clock signal. A row pre-decoding circuit(180) is activated by the control signal, receives an address signal for addressing the row selection lines, and pre-decodes the address signal. A row decoding circuit(300) receives a pre-decoding address signal by the row pre-decoding circuit, and generates a selection signal for selecting one of the row selection lines and the remaining row selection lines. A driving circuit is connected to the row selection lines, activates the row selection line corresponding to the selection signal, and inactivates the row selection lines corresponding to the inactivation signals. The control circuit maintains an activation state of the control signal for a clock cycle wherein the address signal is input.