| 摘要 |
PROBLEM TO BE SOLVED: To reduce time for designing by confirming a relation causing no set up nor a hold error without returning to the preparing circuit of the input signal of flip-flop in the case of describing a synchronous circuit in a hardware description language. SOLUTION: It is judged first whether all the flip-flop cells are selected (step S1). When all the flip-flop cells are not selected, a clock name is added to the output signal of the cells (step S2) and this processing returns to the step S1. Next, it is judged whether all the combination circuit cells are selected (step S3), then processing advances to a step 4 where a clock name is added to the output signal of the cells.
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