| 摘要 |
PURPOSE:To enable the manufacture of a DRAM cell small in an occupying area and high reliability by a method wherein a first capacitor electrode and a second capacitor, which are to be a part of a memory anode and a common electrode respectively, are buried in an element isolating groove and the first capacitor electrode is brought into contact with the side wall of the groove. CONSTITUTION:A MOS transistor and capacitors are integrally formed on a semiconductor substrate 1 provided with an element isolating groove 2 formed on it, and the capacitors are structured by use of the wall of the element isolating groove 2. In this process, a first capacitor electrode 7 and a second capacitor electrode 9 are composed of a conductor film buried in the groove 2, the first capacitor electrode 7 is be in contact with the side wall of the groove 2 and a low concentrated diffusion layer which is connected to a source or the drain 12 of the MOS transistor is formed on the side wall where the first capacitor electrode 7 is contacted. By these processes, a diffusion layer is easily formed on the side wall of a groove, and as an upright MOS transistor is formed overlapping a capacitor, an area that a memory cell occupies can be made small and consequently a DRAM can be improved in integration. |
