INTERNAL CLOCK GENERATOR

摘要

PURPOSE: An internal clock generating circuit is provided to reduce a current consumption from a next cycle during synchronizing an external clock and an internal clock, and also to reduce a current consumption by blocking the driving of unnecessary devices when the phases of the external clock and the internal clock do not coincide. CONSTITUTION: The circuit generates an internal clock synchronized to an external clock, and includes: a clock buffer delaying the external clock and outputting it as the first clock; a main delayer having a delay bandwidth equal to the clock buffer and outputting the delayed second clock in response to the first clock; the first and the second synchronous delay line comprising a plurality of unit delayers(BUD1-BUD11) connected serially to delay the first and the second clock; a number of phase detectors(PDC1-PDCi) latching signals from the unit delayers in an interval where a switching control signal is converted from the first level to the second level, and outputting an active signal when the phase of the latched signal is equal to the phase of the first clock; the first switches which are connected to an output terminal of each unit delayer in the first synchronous delay line, and output an output signal of the corresponding unit delayer as the internal clock in response to the active signal of the second level; a logic control part generating a clock corresponding to the first clock in response to the first clock in an interval where the switching control signal is converted from the first level to the second level; the second switch connected between an output terminal of the logic control part and an input terminal of the main delayer; the third switch connected between the output terminal of the logic control part and an input terminal of the phase detectors; and a switching control part which supplies the first clock to the second synchronous delay line and the input terminal of the phase detectors by turning on the second and the third switch, and blocks a supply path of the first clock by turning off the second and the third switch by the internal clock.