| 摘要 |
A method for manufacturing a semiconductor device having a recess gate is provided to improve a cell threshold voltage and device reliability by preventing loss of a polysilicon electrode due to misalignment of a recess and a gate pattern. A sacrificial layer where a recess forming region is opened is formed on a semiconductor substrate(11). A spacer is formed on a sidewall of the sacrificial layer. The semiconductor substrate is etched by using the sacrificial layer and the spacer as etch masks to form a recess(16). The spacer is removed to open the top and the shoulder region of the recess. A gate dielectric(17) is formed on the surface of the recess. A conductive material layer is formed on the sacrificial layer as the recess is gap-filled. The conductive material layer is planarized to form a first gate electrode(18a). A second gate electrode(19) and a gate hard mask(20) are formed on the first gate electrode to form a gate pattern. The sacrificial layer is removed.
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