Latch and clock structures for enabling race-reduced mux scan and LSSD co-compatibility

摘要

An edge triggered system is provided having a data and scan input includes a latch device having a clock input and an AND gate, coupled to the latch device, structured and arranged to receive a first clock signal and an inverted clock signal to generate a clock to the clock input. A process for operating an edge triggered system having a data and scan input includes forwarding a first clock signal to an input of an AND gate. The method includes inverting a second clock signal forwarded to another input of the AND gate and generating a clock input for a latch device from the AND gate.