Driving method for a semiconductor device with an oxide semiconductor layer between two gate electrodes

摘要

A memory device in which data can be retained for a long time is provided. The memory device includes a memory element and a transistor which functions as a switching element for controlling supply, storage, and release of electrical charge in the memory element. The transistor includes a second gate electrode for controlling the threshold voltage in addition to a normal gate electrode. Further, the off-state current of the transistor is extremely low because an active layer thereof includes an oxide semiconductor. In the memory device, data is stored not by injection of electrical charge to a floating gate surrounded by an insulating film at high voltage but by control of the amount of electrical charge of the memory element through the transistor whose off-state current is extremely low.

主权项

1. A driving method for a semiconductor device, the semiconductor device comprising:
a transistor comprising an oxide semiconductor layer, a first gate electrode, and a second gate electrode; and a memory element comprising a first electrode and a second electrode, the first electrode being electrically connected to the oxide semiconductor layer, wherein the oxide semiconductor layer is interposed between the first gate electrode and the second gate electrode, the driving method comprising: applying a first potential to the first gate electrode, a second potential to the second gate electrode and a fifth potential to the second electrode, respectively, during a first period; and applying a third potential to the first gate electrode, a fourth potential to the second gate electrode and a sixth potential to the second electrode, respectively, during a second period, wherein the first potential is configured to be higher than or equal to the second potential, wherein the first potential is configured to be higher than or equal to the third potential, wherein the second potential is configured to be higher than or equal to the fourth potential, wherein the third potential is configured to be higher than or equal to the fourth potential, wherein the second potential is configured to be lower than or equal to the third potential, and wherein the fifth potential is different from the sixth potential.