| 发明名称 | Memory devices and control methods thereof | ||
| 摘要 | A memory device is provided. The memory device includes a memory device, a plurality of word lines and bit lines, first and second decoders, and a control circuit. The memory array includes memory cells on rows and columns. Each word line is coupled to the memory cells in one row. Each bit line is coupled to the memory cells in one column. The first decoder selects one word line according to an address signal and a first control signal. The control circuit respectively generates the first control signal and the second control signal according to a first clock signal and a second clock signal. In the period during which the first decoder selects the one word line, the second decoder selects at least two bit lines according to the address signal and a second control signal. The memory device performs a read/write operation on the selected bit lines. | ||
| 申请公布号 | US9437284(B1) | 申请公布日期 | 2016.09.06 |
| 申请号 | US201514957311 | 申请日期 | 2015.12.02 |
| 申请人 | Vanguard International Semiconductor Corporation | 发明人 | Chen Jui-Lung;Chen Wei-Ting;Ke Yu-Hsi |
| 分类号 | G11C11/00;G11C11/419;G11C11/418;G11C11/413;G11C11/412 | 主分类号 | G11C11/00 |
| 代理机构 | Birch, Stewart, Kolasch & Birch, LLP | 代理人 | Birch, Stewart, Kolasch & Birch, LLP |
| 主权项 | 1. A memory device comprising: a memory array comprising a plurality of memory cells disposed on a plurality of rows and a plurality of columns; a plurality of word lines, each coupled to the memory cells disposed on one of the plurality of rows; a plurality of bit lines, each coupled to the memory cells disposed on one of the plurality of columns; a first decoder receiving an address signal and a first control signal and selecting one of the plurality of word lines according to the address signal and the first control signal; a second decoder receiving the address signal and a second control signal; and a control circuit receiving a first clock signal and a second clock signal, generating the first control signal according to the first clock signal, and generating the second signal according to the second clock signal, wherein in a period during which the first decoder selects the one of the plurality of word lines according to the address signal and the first control signal, the second decoder selects at least two of the plurality of bit lines according to the address signal and the second control signal, and the memory device performs a read/write operation on the selected at least two of the plurality of bit lines. | ||
| 地址 | Hsinchu TW | ||