发明名称 Thread execution scheduler for multi-processing system and method
摘要 A processing system includes a plurality of processors capable of executing a plurality of threads and supporting at least one of hardware context switching and software context switching. The processing system also includes at least one hardware scheduler capable of scheduling execution of the plurality of threads by the plurality of processors. The at least one hardware scheduler is capable of scheduling execution of the threads by performing instruction-by-instruction scheduling of the threads. <IMAGE>
申请公布号 EP1544737(A1) 申请公布日期 2005.06.22
申请号 EP20040257753 申请日期 2004.12.14
申请人 STMICROELECTRONICS, INC. 发明人 PILKINGTON, CHARLES E.
分类号 G06F9/38;G06F9/48;G06F9/50;(IPC1-7):G06F9/50 主分类号 G06F9/38
代理机构 代理人
主权项
地址