Integrated circuit control based on a first sample value and a delayed second sample value

摘要

An integrated circuit comprises: a first processing stage comprising processing logic for performing a processing operation on an input signal to generate an output signal, wherein the input signal corresponds to an output signal of a previous processing stage; a first sampling element adapted to sample a first value of said output signal synchronously with a clock signal; a second sampling element adapted to sample a second value of said output signal synchronously with a first delayed clock signal; and a first delayed clock signal generator, adapted to selectively generate said first delayed clock signal in response to a control signal generated in said previous processing stage.

主权项

1. An integrated circuit, comprising:
a first processing stage comprising processing logic for performing a processing operation on at least one input signal to generate at least one output signal, wherein said input signal corresponds to an output signal of a previous processing stage; a first sampling element adapted to sample a first value of said output signal synchronously with a clock signal; a second sampling element adapted to sample a second value of said output signal synchronously with a first delayed clock signal; and a first delayed clock signal generator, adapted to selectively enable said first delayed clock signal, in response to a control signal generated in said previous processing stage; and comparison circuitry for comparing said first and said second values of said output signal and generating an error signal if said first and second values are different; wherein, if said first and second values are different, said second value is propagated to a following processing stage.