| 摘要 |
PURPOSE:To enable to shorten the manufacturing term of a semiconductor device and to reduce the cost of the device by using as a base of a master slice of grounding connection line and a power line pattern a wiring pattern of the first layer and treating as the base of the master slice a wafer with respect to the through hole pattern of the first and second layers. CONSTITUTION:A load MOS diffused layer 1, a through hole 3, a gate of a load MOS of the drive MOS diffused layer 17 and a gate 18 of the drive MOS are already formed on the master slice base which is treated up to a diffusion as a wafer. A metal wiring pattern of the first layer shown by the shaded part of the drawing is added to the master slice base. At this time a power source system impedance can be largely reduced by increasing the width of the power wiring part. Further a through hole which connects the metal wirings of the first and second layers shown by the shaded parts of the drawing is added to complete the master slice base. Broken lines 2, 5, 7, 9 designate the metal wirings of the first layer, and a circuit is composed by connecting the through holes which connects the first and second layers. |
