Ferroelectric capacitor test structure for chip die

摘要

A test structure integrated into substantially each circuit die formed on a wafer. The test structure includes a ferroelectric component connected to bond pads of the die so that analog tests can be conducted thereon, and the results of the tests utilized to extrapolate aging and fatigue characteristics of other ferroelectric components in the functional circuits of the die. The ferroelectric test structure can be connected directly to die bond pads, or switchably connected thereto by decoding circuits which share bond pads employed by the other functional circuits of the die.