发明名称 Verification of an extracted timing model file
摘要 A system, apparatus and method for generating and validating extracted timing model files, such as macro library files, are disclosed. A user interface or data template is provided to an engineer that allows for the population of data within particular fields related to timing characteristics of an IP block, cell or core. An extracted timing model file is generated and a validation procedure is performed. This validation procedure may include comparing the information with the file to a test bench have a plurality of test points. In particular, data provided by the engineer is checked against multiple criteria to ensure that this data is valid and/or falls within an appropriate value range constraints. After the validation procedure has completed, the engineer is provided a summary of the validation results.
申请公布号 US2007220462(A1) 申请公布日期 2007.09.20
申请号 US20060376781 申请日期 2006.03.15
申请人 LSI LOGIC CORPORATION 发明人 LINDBERG PETER;KIRCHNER RICHARD K.;BHUTANI SANDEEP
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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