发明名称 PLL CIRCUIT
摘要 PURPOSE:To realize a wide lock range without causing an artificial lock by controlling the frequency of a PLL output signal forcibly to a specific reference frequency when the PLL output signal exceeds a border frequency corresponding to a mode. CONSTITUTION:Period range deviation detecting circuits 36N, 36F, and 36R of a period discrimination circuit 36 detect whether or not period data from the latch circuit 33 of a period data detecting circuit part 30 deviates from respective specific period range in respective operation modes of DAT. If a period range deviation detecting circuit 36N corresponding to current operation mode detects a deviation from said specific period, the output signal of a changeover switch 36S goes up to H and the 8-bit parallel AND gate 37G1 of a period data forcible setting circuit 37 is brought under gate control into a conduction state. Respective mode reference period data generating circuits 37T generate reference period data corresponding to the current mode, so the data are supplied as the period data to the adder 23 of an output clock generating circuit part 20 through the 8-bit parallel OR gate 37B.
申请公布号 JPS6411418(A) 申请公布日期 1989.01.17
申请号 JP19870166527 申请日期 1987.07.03
申请人 SONY CORP 发明人 FUKUDA SHINICHI
分类号 H03L7/10;G11B20/10;H03L7/06 主分类号 H03L7/10
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