Low power programmable image processor

摘要

A convolution image processor includes a load and store unit, a shift register unit, and a mapping unit. The load and store unit is configured to load and store image pixel data and allow for unaligned access of the image pixel data. The shift register is configured to load and store at least a portion of the image pixel data from the load and store unit and concurrently provide access to each image pixel value in the portion of the image pixel data. The mapping unit is configured to generate a number of shifted versions of image pixel data and corresponding stencil data from the portion of the image pixel data, and concurrently perform one or more operations on each image pixel value in the shifted versions of the portion of the image pixel data and a corresponding stencil value in the corresponding stencil data.

主权项

1. A convolution image processor comprising:
a load and store unit configured to load and store image pixel data and stencil data such that the load and store unit provides unaligned access to the image pixel data; a shift register unit configured to load and store at least a portion of the image pixel data from the load and store unit and concurrently provide access to each image pixel value in the portion of the image pixel data; and a mapping unit comprising:
a plurality of interface units each configured to:
generate a plurality of shifted versions of image pixel data from the portion of the image pixel data such that a pattern of the shifted versions of image pixel data is different between each of the plurality of interface units; andprovide corresponding stencil data to the shifted versions of image pixel data; anda plurality of arithmetic logic units (ALUs) configured to concurrently perform one or more operations on each image pixel value in the plurality of shifted versions of the portion of the image pixel data and a corresponding stencil value in the corresponding stencil data provided from a subset of the plurality of interface units, wherein the subset of the plurality of interface units and the one or more operations performed on each image pixel value are programmable.