发明名称 Integrated circuit with efficient testing arrangement
摘要 A read and write control circuit receives (mxn)-bit data output m-bit parallel from a D flip flop, and a q-bit data selection signal such that the output data from the D flip flop is written to memory circuits in units of integral multiples of (x+1) bits in a total of 2q operations, in accordance with a binary value indicated by the data selection signal, where m, n, x and q indicates positive integers (x+1)>m and n>2q, where m, n, x and 1 indicate positive integers and (x+1)>m and n>2q. The data written to the memory circuits is read out in units of integral multiples of (x+1) bits in a total of 2q operations.
申请公布号 US2001043485(A1) 申请公布日期 2001.11.22
申请号 US20000734925 申请日期 2000.12.13
申请人 URAKAMI AKI;NAKAJIMA MICHIO 发明人 URAKAMI AKI;NAKAJIMA MICHIO
分类号 G11C29/38;(IPC1-7):G11C5/00 主分类号 G11C29/38
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