| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, capable of performing verification of error processing operation of system software by a CPU without using special software of error generation software for operating an error generation circuit. <P>SOLUTION: A parity error generation instruction circuit 7 instructs, when an external pality error generation control signal S2 is "1" in system software verification, a parity bit generation circuit 8 to generate a parity bit PB of an error value obtained by inverting a normal value, when a CPU 1 accesses an address which should generate a parity error in a pseudo manner within a memory 5. <P>COPYRIGHT: (C)2008,JPO&INPIT |
