| 发明名称 |
Interaction of transactional storage accesses with other atomic semantics |
| 摘要 |
In a processor, an instruction sequence including, in order, a load-and-reserve instruction specifying a read access to a target memory block, an instruction delimiting transactional memory access instructions belonging to a memory transaction, and a store-conditional instruction specifying a conditional write access to the target memory block is detected. In response to detecting the instruction sequence, the processor causes the conditional write access to the target memory block to fail. |
| 申请公布号 |
US9430166(B2) |
申请公布日期 |
2016.08.30 |
| 申请号 |
US201213650521 |
申请日期 |
2012.10.12 |
| 申请人 |
International Business Machines Corporation |
发明人 |
Frey Bradly G.;Guthrie Guy L.;May Cathy;Williams Derek E. |
| 分类号 |
G06F12/00;G06F3/06;G06F9/46;G06F12/08 |
主分类号 |
G06F12/00 |
| 代理机构 |
|
代理人 |
Russell Brian F.;Bennett Steven L. |
| 主权项 |
1. A method of data processing in a data processing system, the method comprising:
in a processor, detecting an instruction sequence of a particular thread including, in order, a load-and-reserve instruction specifying a read access to a target memory block, an instruction delimiting transactional memory access instructions belonging to a memory transaction, and a store-conditional instruction specifying a conditional write access to the target memory block; and in response to detecting the instruction sequence within the particular thread, the processor causing the conditional write access to the target memory block to fail. |
| 地址 |
Armonk NY US |
