SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS

摘要

Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.

主权项

1. An integrated circuit comprising:
a differential data input buffer having differential inputs and an output; a differential data output buffer having an input and differential outputs; a differential clock input buffer having differential inputs and a clock output; parallel scan paths having stimulus data inputs, response data outputs, and a control input; a test stimulus data register having a serial input coupled to the data input buffer output, a serial header output, parallel outputs coupled to the stimulus data inputs, and a control input; a test command register having a serial input coupled to the header output, a command output, and a control input; a test response data register having parallel inputs coupled to the response data outputs, a serial output coupled to the data output buffer input, and a control input; a test controller having a scan clock input coupled to the clock output, a command input coupled to the command output, and control outputs coupled to the control inputs.