Low voltage transistor and logic devices with multiple, stacked piezoelectronic layers

摘要

A piezoelectronic transistor device includes a first piezoelectric (PE) layer, a second PE layer, and a piezoresistive (PR) layer arranged in a stacked configuration, wherein an electrical resistance of the PR layer is dependent upon an applied voltage across the first and second PE layers by an applied pressure to the PR layer by the first and second PE layers. A piezoelectronic logic device includes a first and second piezoelectric transistor (PET), wherein the first and second PE layers of the first PET have a smaller cross sectional area than those of the second PET, such that a voltage drop across the PE layers of the first PET creates a first pressure in the PR layer of the first PET that is smaller than a second pressure in the PR layer of the second PET created by the same voltage drop across the PE layers of the second PET.

主权项

1. A piezoelectronic logic device, comprising:
a first piezoelectric transistor (PET) device and a second PET device, the first PET device and the second PET device each having a first PE material layer, a second PE material layer, and a piezoresistive (PR) material layer arranged in a stacked configuration, wherein the first PE material layer and the second PE material layer of the first PET device have a smaller cross sectional area than the first PE material layer and the second PE material layer of the second PET device, for each of the first PET device and the second PET device, the first PE material layer is disposed between a first electrode and a second electrode, the second PE material layer is disposed between the second electrode and a third electrode, and the PR material layer is disposed between a fourth electrode and a fifth electrode, and the third electrode and the fourth electrode are separated by an insulating layer, an output terminal is connected between the PR material layer of the first PET device and the PR material layer of the second PET device, the piezoelectronic logic device is an AND gate based on a line voltage being applied to the fifth electrode of the first PET device and the output terminal being connected to both the fourth electrode of the first PET device and the fifth electrode of the second PET device, and the piezoelectronic logic device is a NAND gate based on the line voltage being applied to the fifth electrode of the second PET device and the output terminal being connected to both the fifth electrode of the first PET device and the fourth electrode of the second PET device.