Dual-edge triggered flip-flop circuit with asynchronous programmable reset

摘要

A dual edge-triggered flip-flop that may be programmably reset independent of a clock signal is provided. Using an externally generated reset value, the dual edge-triggered flip-flop may be asynchronously programmed to reset to either a logical high or a logical low. Further, a dual edge -triggered flip-flop that may be set to multiple triggering modes is provided. Using an externally generated enable signal, the dual edge-triggered flip-flop may be set to function as a single edge -triggered or a dual edge-triggered device. Thus, the dual edge -triggered flip-flop may be used in multiple types of computing environments. <IMAGE>