SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

摘要

Thermal resistance is reduced from an element surface of a semiconductor chip to the rear surface of a semiconductor package. Split patterning of a metal is easily carried out, stress produced by a thermal expansion coefficient between silicon and metal is significantly reduced and environment reliability is improved. Low cost is realized by manufacturing a semiconductor package without using a TIM material. A semiconductor package is provided including a semiconductor chip including a first surface and a second surface opposed to the first surface and covered with a resin, an electrode being arranged over the first surface, a first wiring connected to the first surface directly or via a first opening arranged in the resin, and a second wiring connected to the second surface via a second opening arranged in the resin.

主权项

1. A semiconductor package comprising:
a semiconductor chip including a first surface and a second surface opposed to the first surface and covered with a resin, an electrode arranged over the first surface; a first wiring connected to the first surface directly or via a first opening arranged in the resin; and a second wiring connected to the second surface via a second opening arranged in the resin.