Systems and methods for increasing debugging visibility of prototyping systems

摘要

User's register transfer level (RTL) design is analyzed and instrumented so that signals of interest are preserved and can be located in the netlist after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the netlist to ensure that signal values can be accessed at runtime. After that, a place and route (P&R) process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations is field programmable gate array (FPGA) devices. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.

主权项

1. A method to debug a RTL design in an FPGA-based emulation or co-emulation system, the method comprising the steps of:
a. instrumenting the RTL design by inserting at least one dummy module for correlating a set of signals of the RTL design to corresponding gate-level signals; b. synthesizing the instrumented RTL design to generate a gate-level net-list targeting for the emulation or co-emulation system; c. fitting the gate-level net-list into the FPGA devices in the emulation or co-emulation system and generating location information of instances of the gate-level net-list in the FPGA devices; and d. extracting values of gate-level signals corresponding to the set of signals of the RTL design in an emulation or co-emulation run according to the location information of the instances that output the gate-level signals in the emulation or co-emulation system.