| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a phase synchronizing circuit capable of completing phase synchronization in a short time without increasing the occupation area on a chip, the number of gates, and electric power even when an operating frequency range is widened. <P>SOLUTION: The phase synchronizing circuit has a measurement delay array 119 which includes a plurality of delay elements 311, 312, 313, and 314 differing in delay time and inputs a first clock signal 103; a phase comparator array 121 which includes a plurality of phase comparators 109 corresponding to the measurement delay array 119, inputs a signal from the measurement delay array 119 and a second clock signal 104, and measures the transition time difference between the first clock signal 103 and second clock signal 104; and a generation delay array 120 which includes a plurality of delay elements differing in delay time corresponding to the measurement delay array 119, and inputs a signal from the phase comparator array 121 and a third clock signal 105. The delay times of the delay elements are fixed, respectively. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
