| 摘要 |
A decoder circuit for generating mask patterns on a plurality of output terminals in response to multibit binary input number is described using a plurality of two-input multiplexers arranged in parallel paths to form one stage or as a tree structure consisting of several cascaded stages of binary or higher order and controlled by functions of the bits of an input number to produce a logic "1" voltage on a number of output terminals equal to the input number and a logic "0" voltage on the remaining output terminals.
|
