SHARED MEMORY ACCESS SEQUENCE ASSURANCE SYSTEM

摘要

PROBLEM TO BE SOLVED: To provide a shared memory access assurance system which does not have to make subsequent instruction execution wait for the purpose of store sequence assurance in a multiprocessor system having a shared memory. SOLUTION: In a processor 101 on the side assuring a store sequence, when store access 127 started after a store sequence assurance request 133 is reflected in a shared memory 120, a sequence assurance flag 136 is set, and when store access 125 before the request 133 is reflected in the memory 120 or in the cache 124 of another processor 102, it is reset. Meanwhile, in a processor 102 on the side assuring a load sequence, a load sequence assurance request 134 is issued after reading of preceding load access 128 is completed, the load sequence assurance request is completed (135) by such a manner that the sequence assurance flag 136 is reset, and a subsequent load access 130 is started.