Clock generating circuit, semiconductor device including the same, and data processing system

摘要

A method for generating an internal clock signal by a clock generating circuit, including generating the internal clock signal based on an external clock signal, adjusting a phase of the internal clock signal by using a phase control value to synchronize with a phase of the external clock signal based on a phase difference between the external clock signal and the internal clock signal, switching operation modes including a first operation mode in which a phase of the internal clock signal is controlled at a predetermined cycle by updating the phase control value and a second operation mode in which a phase of the internal clock signal is fixed by fixing the phase control value, and the switching includes switching from the second operation mode to the first operation mode in response to a trigger signal.

主权项

1. A method for generating an internal clock signal by a clock generating circuit, comprising:
generating the internal clock signal based on an external clock signal; adjusting a phase of the internal clock signal by using a phase control value to synchronize with a phase of the external clock signal based on a phase difference between the external clock signal and the internal clock signal; and switching operation modes including a first operation mode in which a phase of the internal clock signal is controlled at a predetermined cycle by updating the phase control value and a second operation mode in which a phase of the internal clock signal is fixed by fixing the phase control value, wherein the switching includes switching from the second operation mode to the first operation mode in response to a trigger signal, and the switching includes switching from the first operation mode to the second operation mode in response to a state where the internal clock signal attains a predetermined phase; wherein the trigger signal is generated in response to an output signal of a power detecting circuit, and wherein the power detecting circuit outputs a first level of the output signal when a power supply voltage varies equal to or higher than a reference acceleration and outputs a second level of the output signal when the power supply voltage varies smaller than the reference acceleration, the first and second levels being different from each other.