发明名称 Fast low power level shifters
摘要 In one embodiment, a method for increasing speed of a differential input pair. The method comprises applying a first boost current to a first input of the differential input pair during a transition of a first signal applied to the first input; storing the first boost current; ending the application of the first boost current in response to the stored first boost current exceeding a first threshold; applying a second boost current to a second input of the differential input pair during a transition of a second signal applied to the second input; storing the second boost current; and ending the application of the second boost current in response to the stored second boost current exceeding a second threshold.
申请公布号 US9496873(B2) 申请公布日期 2016.11.15
申请号 US201414451079 申请日期 2014.08.04
申请人 QUALCOMM INCORPORATED 发明人 Li Shengyuan;Mirea Iulian
分类号 H03K19/094;H03K19/0185;H03K3/356;H03K5/24;H03K19/017 主分类号 H03K19/094
代理机构 Haynes and Boone, LLP 代理人 Haynes and Boone, LLP
主权项 1. A circuit comprising: a comparator having a differential input pair comprising a first differential transistor and a second differential transistor; and an input current boost circuit to boost a current of the differential input pair during transition of at least one input to the differential input pair, the input current boost circuit comprising: a first transistor configured to apply a first voltage to the first differential transistor of the differential input pair, the first transistor having a gate coupled to a first input of the at least one input to the differential input pair; a first capacitor coupled to the first transistor to turn off said first transistor in response to charge stored therein from current through said first transistor; a second transistor configured to apply a second voltage to the second differential transistor of the differential input pair, the second transistor having a gate coupled to a second input of the at least one input to the differential input pair; a second capacitor coupled to the second transistor to turn off said second transistor in response to charge stored therein from current through said second transistor; a third transistor coupled in parallel to the first capacitor and having a control terminal coupled to the second input of the differential input pair; and a fourth transistor coupled in parallel to the second capacitor and having a control terminal coupled to the first input of the differential input pair, wherein, in response to a first transition of the first and second inputs to the differential input pair, the first differential transistor turns on, the second differential transistor and the second transistor are off, and the first transistor initially turns on and then turns off as a voltage on the first capacitor increases, and wherein, in response to a second transition of the first and second inputs to the differential pair, the second differential transistor turns on, the first differential transistor and the first transistor are off, and the second transistor initially turns on and then turns off as a voltage on the second capacitor increases, the circuit further comprising a load circuit having inputs coupled to outputs of the differential input pair, the load circuit comprising a plurality of current mirrors, a summing circuit, and an inverter, wherein at least one current mirror comprises a first current mirror transistor coupled between a first reference voltage and a second reference voltage and a second current mirror transistor coupled between the first reference voltage and a third reference voltage.
地址 San Diego CA US