发明名称 Series connected resistance change memory device
摘要 The invention is provided to suppress a current supplied to a storage element so as not to vary for each layer in a semiconductor memory device obtained by connecting a plurality of memory cells in series.;A semiconductor memory device according to the invention includes a plurality of memory cells connected in series between a first signal line and a second signal line, and supplies a different gate voltage to at least two of selection transistors included in the memory cells, respectively (refer to FIG. 2).
申请公布号 US9361978(B2) 申请公布日期 2016.06.07
申请号 US201214421822 申请日期 2012.09.20
申请人 Hitachi, Ltd. 发明人 Shiramizu Nobuhiro;Hanzawa Satoru;Kotabe Akira
分类号 G11C13/00;H01L27/24;H01L45/00 主分类号 G11C13/00
代理机构 Miles & Stockbridge P.C. 代理人 Miles & Stockbridge P.C.
主权项 1. A semiconductor memory device comprising: first and second signal lines; a memory cell which is configured by connecting a transistor and a resistance change element in parallel, and stores information by a state change of the resistance change element; and a driver circuit which supplies a gate voltage to the transistor, wherein a plurality of the memory cells are connected in series between the first and second signal lines, and wherein the driver circuit supplies a different gate voltage to at least two of the transistors included in each of the memory cells, respectively, and wherein the driver circuit, among the gate voltages supplied to the transistors included in each of the memory cells, supplies a lowest gate voltage to the transistor included in the memory cell that is disposed at a position closest to the first signal line, gradually increases a gate voltage to be supplied to the transistor as a position at which the transistor is disposed gets closer to the second signal line, and supplies a highest gate voltage to the transistor included in the memory cell that is disposed at a position closest to the second signal line.
地址 Tokyo JP