Molding compound supported RDL for IC package

摘要

A cylindrical molding compound supported RDL for IC package is disclosed wherein a central cavity is formed in the center of the molding compound. A plurality of metal pillar is embedded in the molding compound, a redistribution layer is configured on bottom of the plurality of metal pillar; at least one passive element such as a capacitor can be mounted in the central cavity. The bottom of the package is adaptive for at least one chip to mount so that the passive element is close to the chip and therefore simultaneous switching noise (SSN) can be reduced to a minimum at the initial first stage when a power is turned on.

主权项

1. A molding compound supported redistribution layer (RDL) structure for an integrated circuit (IC) package, the molding compound supported RDL structure comprising:
a molding compound; a central cavity surrounded by the molding compound; a plurality of metal pillars partially embedded in the molding compound, each metal pillar among the plurality of metal pillars having a bottom end protruded below the molding compound; a redistribution layer having a plurality of bottom metal pads and a plurality of top metal pads; and a chip mounted on bottom of the plurality of bottom metal pads, wherein a density of the plurality of bottom metal pads is higher than the density of the plurality of top metal pads; the bottom end of each metal pillar among the plurality of metal pillars is electrically coupled to a corresponding top metal pad among the plurality of top metal pads; at least one of the plurality of top metal pads is located in the central cavity and is configured for mounting at least one passive element; in a thickness direction of the RDL structure, the redistribution layer is arranged between the chip and the plurality of metal pillars; the redistribution layer further comprises a topmost dielectric layer; and the plurality of top metal pads and the bottom end of each metal pillar among the plurality of metal pillars are embedded in the topmost dielectric layer.