Wiring configuration of a bus system and power wires in a memory chip

摘要

Devices and circuits for wiring configurations of a bus system and power supply wires in a memory chip with improved power efficiencies. The effective resistance on the power supply wires may be reduced by utilizing non-active bus wires as additional power wires connected in parallel with the other supply wires. The non-active bus wires may reduce or prevent parasitic couplings and cross-talk effects between neighboring sensitive wires, thereby improving performance of the chip.

主权项

1. A device comprising:
a first power source line; a first data bus line and a second data bus line; a first configuration bus line arranged between the first data bus line and the second data bus line; a second configuration bus line arranged between the second data bus line and the first power source line; and a second power source line supplied with a second power source different from a first power source applied to the first power source line, wherein the second configuration bus line is arranged between the second data bus line and the second power source line.