Method for forming source/drain contacts during CMOS integration using confined epitaxial growth techniques

摘要

A method includes forming a first confined raised source/drain region between an adjacent pair of first dummy gate structures and a second confined raised source/drain region between an adjacent pair of second dummy gate structures during a same first epitaxial growth process, the first and second confined raised source/drain regions including a first semiconductor material. Thereafter, a replacement metal gate process is performed to replace the pairs of first and second dummy gate structures with respective pairs of first and second replacement gate structures. After the replacement metal gate process is performed, a first contact element is formed to the first confined raised source/drain region, a second epitaxial growth process is performed to form a layer of a second semiconductor material above the second confined raised source/drain region, and a second contact element is formed to the layer of second semiconductor material layer.

主权项

1. A method, comprising:
forming a first confined raised source/drain region between an adjacent pair of first dummy gate structures and a second confined raised source/drain region between an adjacent pair of second dummy gate structures during a same first epitaxial growth process, said first and second confined raised source/drain regions comprising a first semiconductor material; after forming said first and second confined raised source/drain regions, performing a replacement metal gate process to replace said pairs of first and second dummy gate structures with respective pairs of first and second replacement gate structures; after performing said replacement metal gate process, forming a first contact element to said first confined raised source/drain region, performing a second epitaxial growth process to form a layer of a second semiconductor material above said second confined raised source/drain region, and forming a second contact element to said layer of said second semiconductor material layer.