| 摘要 |
<p>PROBLEM TO BE SOLVED: To prevent a read-out defect and excessive erase arising therefrom by gently withdrawing a memory cell source line potential at the time of transition to erase verification from erase pulse impression. SOLUTION: At the time of an erase operation, an erase pulse control signal ERASE and a control signal ERASE 2 turn into an L level and N type transistors(TRs) NM 1, NM 2 are made non-conducting and a P type TR MP 1 is made conducting. An erase voltage VPP is then impressed to a common source line of plural memory cells. At the time of the erase verification transfer from the erase pulse impression, the erase pulse control signal ERASE turns H and the P type TR MP 1 is made non-conducting and the erase voltage VPP impressed to the common source line of the plural memory cells is no more impressed. Simultaneously, the N type TR MN 2 of a small current driving capacity is made conducting and the potential of the memory source line is gently withdrawn down to the grounding potential.</p> |
