发明名称 Metal oxide TFT with improved source/drain contacts and reliability
摘要 A method including providing a substrate with a gate, a layer of gate insulator material adjacent the gate, and a layer of metal oxide semiconductor material positioned on the gate insulator opposite the gate, forming a selectively patterned etch stop passivation layer and heating at elevated temperature in an oxygen-containing or nitrogen-containing or inert ambience to selectively increase the carrier concentration in regions of the metal oxide semiconductor not covered by the etch stop layer, on which overlying and spaced apart source/drain metals are formed. Subsequently heating the transistor in an oxygen-containing or nitrogen-containing or inert ambience to further improve the source/drain contacts and adjust the threshold voltage to a desired level. Providing additional passivation layer(s) on top of the transistor with electric insulation and barrier property to moisture and chemicals in the surrounding environment.
申请公布号 US9412623(B2) 申请公布日期 2016.08.09
申请号 US201514833462 申请日期 2015.08.24
申请人 CBRITE INC. 发明人 Yu Gang;Shieh Chan-Long;Xiao Tian;Foong Fatt
分类号 H01L21/383;H01L29/786;H01L29/49;H01L29/66;H01L23/00;H01L21/8234;H01L21/4763;H01L21/324;H01L21/321;H01L21/477;H01L21/428;H01L29/45 主分类号 H01L21/383
代理机构 Parsons & Goltry 代理人 Parsons Robert A.;Goltry Michael W.;Parsons & Goltry
主权项 1. A method of forming ohmic source/drain contacts in a metal oxide semiconductor thin film transistor comprising the steps of: providing a substrate with a gate, a layer of gate insulator adjacent the gate, and a layer of metal oxide semiconductor material positioned on the layer of gate insulator opposite the gate; forming a patterned etch stop passivation layer on selected portions of the layer of metal oxide semiconductor material defining source/drain areas and heating at an elevated temperature in an oxygen-containing or nitrogen-containing or inert ambience to selectively increase the carrier concentration in the source/drain areas of the metal oxide semiconductor layer not covered by the etch-stop layer; depositing overlying and spaced apart source/drain metals on the source/drain areas to make ohmic source/drain contacts in a thin film transistor configuration; subsequently heating the thin film transistor on the substrate in an oxygen-containing or nitrogen-containing or inert ambience to improve the source/drain contacts and adjust the threshold voltage to a desired level; and providing additional passivation layer(s) on top of the thin film transistor with electric insulation and barrier property to moisture and chemicals in the surrounding environment.
地址 Goleta CA US