Scalable interconnect structures with selective via posts

摘要

Interconnect structures including a selective via post disposed on a top surface of a lower level interconnect feature, and fabrication techniques to selectively form such a post. Following embodiments herein, a minimum interconnect line spacing may be maintained independent of registration error in a via opening. In embodiments, a selective via post has a bottom lateral dimension smaller than that of a via opening within which the post is disposed. Formation of a conductive via post may be preferential to a top surface of the lower interconnect feature exposed by the via opening. A subsequently deposited dielectric material backfills portions of a via opening extending beyond the interconnect feature where no conductive via post was formed. An upper level interconnect feature is landed on the selective via post to electrically interconnect with the lower level feature.

主权项

1. An integrated circuit (IC) interconnect structure, comprising:
a conductive interconnect feature embedded within a first dielectric material disposed over a substrate; a via recess overlapping a sidewall of the interconnect feature; a conductive via post disposed in direct contact with a top surface of the interconnect feature; and a second dielectric material disposed within the via recess and in direct contact with the sidewall of the interconnect feature, wherein the via recess defines a non-planarity in the first dielectric material, or in an intervening dielectric material disposed between the first dielectric material and the second dielectric material.