Logic circuit, processing unit, electronic component, and electronic device

摘要

A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

主权项

1. A logic circuit comprising a first circuit and a second circuit,
wherein the first circuit includes first to n-th input terminals and a first output terminal, where n is an integer of 2 or more, wherein the second circuit includes an (n+1)th input terminal, a first node, a first capacitor, and first to third transistors, wherein the first circuit is configured to select one of the first to n-th input terminals and to output data whose logic level is the same as a logic level of the selected input terminal from the first output terminal, wherein the first capacitor is electrically connected to the first node, wherein the first transistor is configured to control electrical connection between the (n+1)th input terminal and the first input terminal, wherein the second transistor is configured to control electrical connection between the first output terminal and the first node, wherein the third transistor is configured to control electrical connection between the first node and the first input terminal, wherein a gate of the first transistor is electrically connected to a gate of the second transistor, and wherein the second transistor and the third transistor each include a semiconductor region comprising an oxide semiconductor layer.