发明名称 |
TRANSMISSION DEVICE AND METHOD FOR CONTROLLING FIFO CIRCUIT |
摘要 |
PROBLEM TO BE SOLVED: To suppress generation of a signal error due to variations in phase of a writing clock without increasing the size of a memory of a FIFO circuit.SOLUTION: The transmission device includes: a writing pointer controlling unit generating a writing pointer, using a writing clock regenerated from a data signal; a reading clock generating unit generating a reading clock; a reading pointer controlling unit generating a reading pointer, using the reading clock; a memory in which a data signal is written into a bit specified by the writing pointer and a data signal is read from a bit specified by the reading pointer; a detecting unit detecting a usage rate of the memory based on difference between the writing pointer and the reading pointer; and a frequency controlling unit generating a frequency control signal changing the frequency of the reading clock if the usage rate is out of an acceptable range specified in advance.SELECTED DRAWING: Figure 2 |
申请公布号 |
JP2016130921(A) |
申请公布日期 |
2016.07.21 |
申请号 |
JP20150004530 |
申请日期 |
2015.01.13 |
申请人 |
FUJITSU OPTICAL COMPONENTS LTD |
发明人 |
KUWATA NAOKI |
分类号 |
G06F13/38;G06F1/12;G06F13/42 |
主分类号 |
G06F13/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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