| 摘要 |
PROBLEM TO BE SOLVED: To enhance error detection rate in a programmable logic device.SOLUTION: By loading the constitution information to the configuration memory of a FPGA10, arithmetic circuits L1-L3 and a verification circuit 21 are formed. The arithmetic circuits L1-L3 have the same calculation function, but the combination of circuit block is different from each other. The arithmetic circuits L1-L3 are a combination of circuit blocks using DSP blocks to the maximum, and the arithmetic circuit L2 is a combination of circuit blocks other than the DSP block. The arithmetic circuit L1, L2 use a block RAM as a data holding memory, and the arithmetic circuit L3 uses a distributed RAM as the data holding memory. Each arithmetic circuit L1-L3 receives input data X, respectively, and outputs arithmetic result data V1-V3. The verification circuit 21 verifies presence or absence of an error, by comparing the arithmetic result data V1-V3.SELECTED DRAWING: Figure 2 |
