| 摘要 |
PROBLEM TO BE SOLVED: To accurately write and read data at a low voltage even during parallel execution of read access and write access in a multiport SRAM cell. SOLUTION: A power supply control circuit (PCK0-PCKn) is provided corresponding to a memory cell array, and the voltage level of a cell source line (VDM, VSM) is set according to an access mode during the parallel execution of the read access and the write access. COPYRIGHT: (C)2008,JPO&INPIT
|
