发明名称 Via Corner Engineering in Trench-First Dual Damascene Process
摘要 An integrated circuit structure includes a first dielectric layer, an etch stop layer over the first dielectric layer, and a second dielectric layer over the etch stop layer. A via is disposed in the first dielectric layer and the etch stop layer. A metal line is disposed in the second dielectric layer, wherein the metal line is connected to the via. The etch stop layer includes a first portion having an edge contacting an edge of the via, wherein the first portion has a first chemical composition, and a second portion in contact with the first portion. The second portion is spaced apart from the via by the first portion, and wherein the second portion has a second chemical composition different from the first composition.
申请公布号 US2016336221(A1) 申请公布日期 2016.11.17
申请号 US201615223118 申请日期 2016.07.29
申请人 Taiwan Semiconductor Manufacturing Company, Ltd. 发明人 Ting Chih-Yuan
分类号 H01L21/768;H01L23/532;H01L23/528;H01L23/522 主分类号 H01L21/768
代理机构 代理人
主权项 1. A method comprising: forming a first dielectric layer; forming a dielectric etch stop layer over the first dielectric layer; forming a second dielectric layer over the dielectric etch stop layer; etching the second dielectric layer to form a via opening, wherein a portion of the dielectric etch stop layer is exposed through the via opening; performing a treatment on the dielectric etch stop layer, wherein a portion of the dielectric etch stop layer exposed through the via opening and a ring portion of the dielectric etch stop layer are treated to form a treated portion, and the ring portion encircles the exposed portion; and performing an etching step to form a trench in the second dielectric layer, wherein during the etching step, the via opening extends down into the first dielectric layer, and both the exposed portion and the ring portion are etched during the etching step.
地址 Hsin-Chu TW