发明名称 メモリアクセス制御装置、及び製造方法
摘要 A memory access control device including: a bit position information storage unit storing bit position information indicating one or more bit positions in a bit sequence of a predetermined length; a reading unit configured to attempt to read a bit sequence from the range specified by the logical address received by the logical address receiving unit, thereby receiving a first bit sequence from the external memory in units of the predetermined length, the first bit sequence being composed of bits that are larger in number than bits stored in the range specified by the logical address; a bit sequence extracting unit configured to extract one or more bit sequences from the first bit sequence at the one or more bit positions indicated by the bit position information in units of the predetermined length.
申请公布号 JP6011953(B2) 申请公布日期 2016.10.25
申请号 JP20150146438 申请日期 2015.07.24
申请人 パナソニックIPマネジメント株式会社 发明人 森本 高志;橋本 隆
分类号 G11C29/00;G11C5/00 主分类号 G11C29/00
代理机构 代理人
主权项
地址