Diagnosis and debug with truncated simulation

摘要

Patterns used to detect a failure in a semiconductor chip are analyzed to determine a subset of logic in a design where a semiconductor chip, fabricated based on the design, contains a fault in the subset. Parts of the semiconductor chip can be pre-calculated to identify a key subsection of logic, based on the patterns, with that subsection being stored in a computer readable file. Good-machine simulation is performed on the subsection of logic using truncated rank-ordered simulation. The results are compared to the results of the testing of the physical semiconductor chip.

主权项

1. A computer-implemented method for design analysis comprising:
determining one or more patterns, from patterns used to test a semiconductor design, which cause a physical semiconductor chip, based on the semiconductor design, to fail in operation; identifying a subset of logic within the design where the fail occurred based on the one or more patterns which cause the physical semiconductor chip to fail in operation; generating a truncated list of nodes and logic based on the subset of logic, wherein the truncated list includes a list of observe nodes and a list of pass-through cells; and performing simulation on the subset of logic using the one or more patterns and the truncated list.