| 摘要 |
PROBLEM TO BE SOLVED: To select a phase clock optimal for input data from among a plurality of clock signals having a plurality of phase relationships by using the smaller number of gate logics. SOLUTION: Pixel data 201 are converted into phase-shifted PWM signals 260A, 260B, 260C and 260D corresponding to phase 0°, phase 90°, phase 180°, phase 270°clocks from a PLL (Phase Lock Loop) module 235 and outputted by PWM pulse generators 300A, 300B, 300C and 300D. A selector 220 selects one of output phase-shifted PWM signals based on which one of aligned beam detection signal 275A, 275B, 275C and 275D from a control logic 230 is first shifted, and a PWM output signal 260 can be generated on the basis of the selected phase-shifted PWM signal. COPYRIGHT: (C)2008,JPO&INPIT
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