| 摘要 |
PROBLEM TO BE SOLVED: To accurately compute a critical area without depending upon a pattern layout in a method for verifying the semiconductor pattern layout. SOLUTION: In a step ST01, AA-pattern data of a MOS transistor and gate-pattern data are superposed. In the steps ST02 and ST03, potential information is added to the AA-pattern data divided by the gate-pattern data. In the step ST04, a first critical area to a short circuit between different-potential patterns and a second critical area to the short circuit between different-potential patterns crossing over a gate pattern are generated. In the step ST05, the first and second critical areas are combined, and a final critical area is extracted. COPYRIGHT: (C)2008,JPO&INPIT
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