发明名称 |
PREFETCHING WEIGHTS FOR USE IN A NEURAL NETWORK PROCESSOR |
摘要 |
A circuit for performing neural network computations for a neural network, the circuit comprising: a systolic array comprising a plurality of cells; a weight fetcher unit configured to, for each of the plurality of neural network layers: send, for the neural network layer, a plurality of weight inputs to cells along a first dimension of the systolic array; and a plurality of weight sequencer units, each weight sequencer unit coupled to a distinct cell along the first dimension of the systolic array, the plurality of weight sequencer units configured to, for each of the plurality of neural network layers: shift, for the neural network layer, the plurality of weight inputs to cells along the second dimension of the systolic array over a plurality of clock cycles and where each cell is configured to compute a product of an activation input and a respective weight input using multiplication circuitry. |
申请公布号 |
US2016342892(A1) |
申请公布日期 |
2016.11.24 |
申请号 |
US201514844670 |
申请日期 |
2015.09.03 |
申请人 |
Google Inc. |
发明人 |
Ross Jonathan |
分类号 |
G06N3/08;G06N3/063 |
主分类号 |
G06N3/08 |
代理机构 |
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代理人 |
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主权项 |
1. A circuit for performing neural network computations for a neural network comprising a plurality of layers, the circuit comprising:
a systolic array comprising a plurality of cells; a weight fetcher unit configured to, for each of the plurality of neural network layers:
send, for the neural network layer, a plurality of weight inputs to cells along a first dimension of the systolic array; and a plurality of weight sequencer units, each weight sequencer unit coupled to a distinct cell along the first dimension of the systolic array, the plurality of weight sequencer units configured to, for each of the plurality of neural network layers:
shift, for the neural network layer, the plurality of weight inputs to cells along the second dimension of the systolic array over a plurality of clock cycles, where each weight input is stored inside a respective cell along the second dimension, and where each cell is configured to compute a product of an activation input and a respective weight input using multiplication circuitry. |
地址 |
Mountain View CA US |