HIGH SPEED DATA TRANSFER USING CALIBRATED, SINGLE-CLOCK SOURCE SYNCHRONOUS SERIALIZER-DESERIALIZER PROTOCOL

摘要

An electronic system, comprising a first semiconductor device, a second semiconductor device, a clock circuit, and a plurality of independently adjustable calibration circuits connected in each of the plurality of serial data paths. The first semiconductor device may comprise a plurality of Serializer-Deserializer interfaces. The second semiconductor device may comprise a plurality of serial data interfaces coupled to the plurality of Serializer-Deserializer interfaces to provide a plurality of serial data paths between the first semiconductor device and the second semiconductor device. The plurality of Serializer-Deserializer interfaces and the plurality of serial data interfaces may be clocked from a clock signal derived from the clock circuit. The plurality of independently adjustable calibration circuits may be configured to compensate for timing differences across the plurality of serial data paths.

主权项

1. An electronic system, comprising:
a first semiconductor device comprising:
a plurality of Serializer-Deserializer interfaces; a second semiconductor device comprising:
a plurality of serial data interfaces coupled to the plurality of Serializer-Deserializer interfaces to provide a plurality of serial data paths between the first semiconductor device and the second semiconductor device; and a clock circuit; a plurality of independently adjustable calibration circuits connected in each of the plurality of serial data paths, wherein:
the plurality of Serializer-Deserializer interfaces and the plurality of serial data interfaces are clocked from a clock signal derived from the clock circuit, andthe plurality of independently adjustable calibration circuits are configured to compensate for timing differences across the plurality of serial data paths.